The present invention relates to a layout design technique for integrated circuits, and more particularly, it relates to methods of determining a line path and estimating delay in rough routing of semi-custom LSIs such as an ASIC.
In the recent manufacturing technique for semiconductor integrated circuits, transistors and lines have been more and more refined. In accordance with the refinement, the delay time of a transistor itself tends to be decreased. However, since the capacitance between adjacent lines is increased due to the refinement of the lines, the output load capacitance of a cell cannot be always decreased, and hence, the proportion of delay depending upon the line capacitance is relatively increased in the delay of the entire integrated circuit.
Accordingly, in order to guarantee an operation timing, the recent layout design for an integrated circuit requires a method of precisely estimating a line capacitance in consideration of an adjacent line and definitely determining a line path that satisfies a timing constraint.
Conventional methods of determining a line path include the following:
As a first conventional method, after a routing pattern is generated on the basis of detailed routing for determining lines in detail, an adjacent routing pattern is searched for with regard to each line so as to calculate a line capacitance generated between the adjacent lines (Japanese Laid-Open Patent Publication No. 6-120343).
As a second conventional method, in a rough routing procedure, a delay time of each line is estimated on the basis of a virtual line length and a line capacitance attained when the line is assumed to be allocated to an interconnect layer having the maximum line capacitance per unit length (hereinafter referred to as the "unit capacitance"), so as to extract a net against a timing constraint, and this net is allocated to another interconnect layer for satisfying the timing constraint (Japanese Laid-Open Patent Publication No. 5-143692).
However, the conventional methods of determining a line path have the following problems:
In the first conventional method, since a line capacitance is calculated in consideration of the influence of an adjacent line after completely generating the routing pattern in detail on the basis of the detailed routing, when there is a timing error, it is very difficult to remove the timing error by modifying the routing. Specifically, the amount of data to be dealt with for modifying the routing is so large that the process takes a long period of time, and in some cases, the calculating process cannot be converged and the routing cannot be modified.
Alternatively, in the second conventional method, since a line is assumed to be allocated to an interconnect layer with the maximum unit capacitance in the net against the timing constraint, the line capacitance is likely to be excessively estimated. Also, since an adjacent line is not considered in the estimation of the line capacitance, even when no timing error is caused in the rough routing process, a timing error can be occasionally caused due to an adjacent line after detailed routing. Accordingly, a netlist itself should be changed for the modification for eliminating the timing error.